In an integrated circuit (IC) device having an adjustable-width signaling interface, a selectable number of input/output (I/O) pins may be used to convey information-bearing signals, thus enabling an IC to be configured according to system requirements. In the context of a memory system, for example, a single memory IC having an adjustable width data interface that ranges from N I/O pins to N/M (N divided by M) I/O pins can be used to support the various pin widths demanded by different industry sectors, and can also be used to support capacity expansion techniques in which the number of signaling links allocated to a given memory IC is diluted (or reduced) as the memory IC population is increased.
Unfortunately, width adjustability has been limited to relatively low max/min width ratios (i.e., ratio of N to N/M, and thus low values of M) due to practical constraints involved with laterally transferring the data along the interface between internal registers and the I/O pins. More specifically, each halving of the interface width typically requires a lateral transfer bandwidth equal to the link bandwidth itself—a transfer bandwidth that begins to consume an impractically large volume of interconnect resources as the max/min width ratio grows larger than two. Moreover, signal propagation delay associated with the transfer tends to increase with the square of the physical transfer distance which itself is typically proportional to the max/min width ratio.